Wednesday, December 30
Apti Q
அபியின் அப்பாவுக்கு முன்று பெண் குழதைகள் .. முதல் பெண் குழந்தை பெயர் சுபா ... இரண்டவது பெண் குழந்தை பெயர் திவ்யா .. therefore முன்றாவது பெண் குழந்தை நேம்?????
Tuesday, December 29
Verilog HDL vs. VHDL
Verilog HDL vs. VHDL
For the First Time User Bill Fuchs / President & CEO - Simucad / Chairman BoD - OVI Introduction The search for the perfect HDL is like the search for the perfect car, the perfect home or maybe even the perfect relationship. It probably doesn't exist. With HDLs, it is no different. The decision of which language to choose is based on a number of important baseline requirements (factors), particularly for the first time user. For argument's sake, let's define the first time user as one who has not used HDLs before and is considering the use of an HDL for their current or next design project. For the most part, the use of an HDL based design strategy should improve the first time user's productivity, although in most cases this may not be realized for some time. Basic Factors for Choosing an HDL Let's explore some of those factors. The most important factor is really a question, Why should I implement an HDL in my design process, and what benefits will using an HDL provide for me? There should be a good, solid reason for the implementation of an HDL-based design methodology. If not, the designer, the design and maybe even the company may be impacted adversely. If time to market is an important consideration then it should also be an integral part of the determination process. Although we have all read about the benefits that can be realized by utilizing an HDL, there are many issues that must be taken into account. The primary reason for using an HDL should be an overall gain in productivity, although this may be difficult to quantify. If you can't rationally predict a gain in productivity or if a sizable loss of productivity is highly probable, don't give up the HDL investigation. Just remember, it is important to recognize that a productivity gain may not be recognizable until a number of designs have passed through the HDL based design process, and even then it may not assume an easily measurable form. Often times new HDL based designs are so different from the designs of the past that it becomes an apples to oranges comparison and productivity gains cannot be readily determined. Do not adopt an HDL based design strategy, just to possess so called state-ofthe- art tools or to move into the supposed world of 21st century design. Some designs are just too simple for using an HDL, and some may be inconsistent with 2 the strong points of HDLs. Nonetheless, the most important factor will always be, why adopt an HDL and, what are the specific benefits of using an HDL? Ease of Use The next most important factor is usability, which can be broken down into separate categories. Category A, Ease of Learning, this relates to how easy it is to learn the language without prior experience with HDLs. It also means how simple is it to convert a designers existing logic design know-how into realizable HDL-based models in a practical timeframe. Category B, Ease of Use, means once the first time user has learned the language, how easy will it be to use the language for their specific design requirements. Category C, Future Usability, means although the language may be sufficient for today's requirements, what about tomorrow's requirements. This is based on the language's long term usability potential as defined by your future design requirements and not a tool vendors future positioning of the language or the tools. Quote from E.E. Times When I worked at HP Roseville, I remember taking my first Synopsys training class. The instructor from Synopsys kept telling us that we were making a grave mistake using Verilog and that EVERYONE who was anyone was using VHDL. (I actually was worried at the time we had chosen the wrong language, and that he was really unbiased. As I look back, I'm glad we chose Verilog, especially when teaching new engineers and when getting our SW/FW folks (who eat/sleep/breathe "C") to understand the HDL I have written. I would really encourage any new HDL designer to choose Verilog rather than VHDL, since it is much easier to learn, use and eventually master. Scott C. Petler Next Level Communications, Inc. Adaptability Another important factor is how the HDL can integrate into the current design environment and the existing design philosophy. Every user has developed certain design methodologies and strategies, which, for better or for worse, have 3 worked successfully for their designs. The adoption of an HDL-based methodology should afford the designer some gains in productivity but not at the expense of completely changing all of their original methodologies and strategies. Essentially, one should not adopt an HDL strategy at the expense of sacrificing everything else. The chosen HDL-based strategy should blend with the existing design tools and methodologies, while providing assistance in moving it into a mode where greater productivity gains can be realized. In the real world, this means taking a structural implementation, usually in gates or transistors, (switch level) and moving it up the ladder of design abstraction to a behavioral (RTL level) implementation. The HDL should support all of the necessary constructs that can enable the first time designer to use this type of methodology for his designs in a reasonable timeframe. Quote from E.E. Times In a previous life, I worked as an onsite applications engineer for an ASIC vendor. The customer that I supported was developing 17 ASIC's for a large program. The customer chose to develop some of the designs in VHDL and others in Verilog. All were synthesized using Synopsys. The smallest design was 15K gates, the largest was 100K gates. I interviewed the design teams to gather some interesting statistics. Conclusions were: 1) Designs done in Verilog were, without fail, completed faster than those done in VHDL. (In terms of gates/manweek.) 2) Adding designers to VHDL and Verilog based designs SLOWED the gates/manweek metric, but adding designers to VHDL-based designs had a greater negative impact. (Probably due to data-typing issues.) 3) Single or dual-person design teams out performed all others. The designers (80) were of various experience levels, working in groups of 2 to 10. Measuring from the end of (the) specification (cycle) to final signoff, the highest performing was a Verilog team at 1500 gates/manweek, the lowest (performing) was a VHDL team with 8 gates/manweek! ASIC Foundry Engineer, Anonymous The Reality Factor The last factor is one of general reality. Does the HDL support the specific technical methodologies and strategies that the first time user requires? Due to a first time users experience with gate and transistor level structures, this usually 4 means, working with structural elements and other related attributes including detailed timing constructs. Does the HDL support timing? Are the libraries or models I use available for the HDL based tools? Are timing-based models available from multiple sources? Are tools available in my affordable price range that can support my intended use of the HDL? Are there resources to help me obtain the optimum results from my usage of the HDL? Will the HDL and these tools help me achieve my desired productivity and “time to market” goals? Now that we have a preliminary set of criterion let's look at two HDLs, Verilog HDL and VHDL, and see how they measure up to this initial set of requirements. As a first time user, it is important to understand a little background on the two languages. Often times knowing the origin gives a solid basis as to what the original developers intended when they composed the HDL. VHDL -- Language by Committee VHDL was developed by committee intended for documenting digital hardware behaviorally. The intent for the language was solely for the explicit purpose of documentation. It originated out of the VHSIC (Very High Speed Integrated Circuit) Program as a part of a US DOD (Department of Defense) Project in 1981. In 1983 the DOD awarded a contract to Intermetrics, IBM and Texas Instruments. It was known as VHDL 7.2 and was completed in 1985,. Its selection by the DOD as a documentation language for its digital designs has provided the initial momentum. In an effort to focus its use on practical applications and to expand beyond the use as simply a documentation language, it has been through numerous iterations. During this refinement process it has become IEEE standard 1076 in 1987. Although it was adopted by many EDA companies and carried strong support from the European electronics market, VHDL had significant deficiencies. The deficiencies were most evident at the gate and transistor levels. In addition,
there was no facility for handling timing information. Due to these crucial,
limitations, VHDL did not make a major impact on the design community,
although it was heavily promoted in the trade journals and by EDA companies
trying to distance themselves from Cadence. The design community proposed a
methodology to help VHDL move towards a more useful design language. This
initial effort was called the VHDL Initiative Towards ASIC Libraries, or VITAL.
VITAL was the supposed to be the specific methodology for describing VHDL
gate level structures and timing. Today VHDL is going through the steps of
approving Vital 2.2b as an extension and standard based on 1076. In 1992, the
5
IEEE formulated IEEE standard 1164 - 1992 (MVL-9) as a recommended
practice for modeling guidelines for use in various simulation environments.
EDA Tool Support
Any language is only as good as the tools that support it, and VHDL is no
exception. Only after VHDL was adopted by a number of the EDA companies as
their exclusive HDL did the language become useful as a practical design tool.
Although many of these EDA companies had their own proprietary HDLs
integrated within their own simulation environments, they elected to adopt VHDL.
The reason these EDA companies did not adopt Verilog HDL is that they all
have a basic philosophy which states they must own all of their core technology.
An HDL, any HDL would be the cornerstone of an EDA companies technology.
The schematic editor would use it as would the ESDA tool, the simulation
environment, synthesis tools, emulation tools, display tools, almost every phase
of the design cycle would be drastically effected by the chosen HDL. These
EDA companies selected VHDL because Verilog HDL was the intellectual
property of Gateway Design Automation, and eventually was acquired by
Cadence. Cadence’s ownership of Verilog HDL made it even more essential for
these EDA companies to support VHDL and distance themselves from any
strategic ties to Verilog HDL and any potential competitive control from
Cadence.
Quote from E.E. Times
Actually, an interesting look at VHDL vs. Verilog was accidentally done in our
graduate level logic synthesis course. We recently got Synopsys Design Compiler,
Synopsys VHDL and Cadence Verilog-XL. While The rest of the class did their
projects in VHDL, my lab partner and I did ours in Verilog. (We learned Verilog on
our own; unlike my VHDL classmates, we had no class lectures, no T/A help, no
professorial help.)
The results of this were overwhelmingly in favor of Verilog as a tool to teach HDLs. Our final project, a 7500 gate, 35nsec RISC processor was ~25 pages of Verilog. The VHDL people all ended up rushing near the end to just make something which worked and could be synthesized. Several groups failed at this altogether! (Whereas our project grew so large in functionality, our only problem was finding a workstation which had enough memory to handle the synthesis of the top level design.) The general comments in talking to the other students was they spent a majority of their timing fighting VHDL/Synopsys. We spent a majority of our time doing design work, and optimization. Jeff Echtenkamp 6 Iowa State University Verilog HDL -- A Language for Designers Verilog HDL comes from the commercial world and was developed as part of a complete simulation system. It was also developed to be used for describing digitally based hardware systems. Verilog HDL made its mark by allowing designers to represent their designs in the familiar method (gate and switch level descriptions) as well as abstractly or behaviorally. By allowing this top down or bottom up methodology it afforded the designers a learning period to get comfortable while at the same time achieving significant productivity gains. During Verilog HDL's formative years, it was improved on a regular basis by taking the users' input for technology requests and enhancing and modifying the language for practical designer requirements in a timely manner. When Cadence purchased the Verilog assets from Gateway in 1989, Verilog HDL and the and simulation tools in the market. Verilog was described by the users as "the best in its class". In 1990 Verilog HDL was placed into public domain and since then end-users, semiconductor companies and EDA companies have directly benefited from this open availability. Today there are more than 40,000 qualified Verilog HDL users; 250 ASIC, FPGA and other types of models and libraries available; more than 300 universities teach the language as part of their advanced EE programs; and now more than 75 companies offer Verilog HDL products and services. In 1990, Open Verilog International (OVI) assumed responsibility for the public domain assets that comprise Verilog HDL. They have improved the Verilog HDL documentation set and enhanced and extended the language for use with new technologies. OVI applied for IEEE standardization which it will formally receive in December of 1995. The Technical Coordinating Committee enabled four separate technical projects in 1995. These are as follows; Verilog Analog Behavioral Language Standard, ASIC Library Modeling Standard, Delay Calculation Standard and a Verilog HDL language extension and enhancement subcommittee. All of these projects will be submitted to the IEEE within the next two years. Quote from E.E. Times I have spent most of my design life (last 4 years) working on VHDL designs. Recently, I have been forced into the Verilog camp by a vendor. My initial concerns that Verilog would not have the functionality that I needed have been proven wrong. Verilog does what I need better - and the simulators are faster than VHDL simulators. Since VHDL was driven mostly by the government which has no interest in the productivity of the designers, it is not surprising to see your results from the contest. 7 VHDL syntax hinders progress and does not improve the robustness or quality of the design. The behavioral compilers, not VHDL, make the most sense for doing even more sophisticated design work. Please don't make be go back to VHDL! Robert Rust Hewlett Packard Boise Printer Division Technical Mis-Match-up The two languages have different technical strengths which significantly differentiates their market focus. Verilog HDL's technical strength is in its ability to represent digital hardware (and analog hardware in Verilog-A) the way a hardware designer would envision and implement the design. Verilog HDL has built-in predefined hardware net types (wire, wor, wand, tri, etc.) thus eliminating the interpretation issues inherent in VHDL. Verilog HDL also has gate and switch level modeling, enabling ASIC foundries to accurately represent their cell libraries. More complex modeling like pullups / pulldowns, dynamic charge sharing and signal strength can be accurately modeled with relative ease. Verilog HDL affords the designer a simple language syntax and structure. This capability, unlike VHDL, allows the designer to learn the language quickly and develop more concise and effective models. The ease of use of Verilog HDL translates well into the supported simulation environments and their performance characteristics. VHDL models, on the other hand are inherently indecisive, due to programmability and therefore do not provide a framework to achieve adequate performance from their respective simulation tools. We have seen a recent test of this fact from NEC. NEC developed VHDL libraries for their complex ASICs at the gate level using the Vital 2.2b specification. NEC’s experience with HDL’s and model and library development is extensive. The resultant NEC, VHDL, Vital 2.2b libraries required almost 50X more memory to run than the equivalent Verilog HDL description of the same model. This translates into simulation speeds that are 50 to 100 longer than the same Verilog HDL-based simulation run. The resultant performance is commercially unacceptable. Verilog HDL was designed with features (such as global variables) which are required to model the system's environment. Therefore, it is easy to model a "test bed" using Verilog HDL. This capability is a significant deficiency in VHDL. Verilog HDL also permits the use of monitoring code within a model to insure that errors are caught early in the design process. The modeling code has no physical analogy and simply cannot be handled easily in VHDL. Quote from E.E. Times 8 My transition from VHDL to Verilog came about 2 years back when I worked on a design which was about 45K gates. I learned Verilog as the ASIC Vendor we worked with was only comfortable doing a final signoff in Verilog rather than VHDL. With the flavor of both the languages, here are my comments: 1) VHDL is a good structured HIGH level language but I feel Verilog is closer to actual hardware which is being designed. 2) As far as behavioral goes, I rank VHDL at par with Verilog, but when it comes to RTL, I consider Verilog has the edge over VHDL as far as the time to market ( i.e. meeting the design schedule is concerned.) As far as the contest goes, I think Verilog has again proved the point. Yes, with VHDL you can achieve the same target but at the cost of design time and support. In the present industry, time to market a product is the key to success. If a particular market window is missed, the ASIC and the man-months spent on it are a sheer waste. I strongly feel that given the choice and the design time I would opt for Verilog. Subhodip Ghosh Western Digital Corp. Timing is Everything Verilog HDL provides module paths and conditional specification of path delays through the specify block. This critical element of the language is important because neither lumped or distributed timing models are complete by themselves. The Standard Delay Format (SDF) in Verilog HDL provides the essential back annotation facility for loading post route delay calculations, a utility not available in VHDL. When the technical strengths of gate and switch level modeling and specific timing constructs are considered it is no wonder that almost every ASIC foundry on the planet “sign-off” for production on all their designs using Verilog HDL. Presently VHDL models or simulation is not used for sign-off by any semiconductor company. Today ASIC library support for Verilog HDL is impressive, with over 250 libraries (with full timing parameters) from more than 40 different companies, available to users of Verilog HDL. Another important fact, more than 70% of all semiconductor companies worldwide use Verilog HDL for their “Golden Simulation” requirements. There are other areas of technical importance that affords Verilog HDL some significant benefits when compared to VHDL. The ability to reference a signal across module boundaries is necessary because it provides an arbitrary access to variables in the model. This connection can be provided without any structural requirements such as declaring ports. In addition, Verilog HDL supports "named events" that provide a much needed abstraction at the high 9 level where "events occur" and "events get consumed". This use of the language is extremely beneficial when modeling the "test bed environment" of a design. VHDL relies solely on communicating through signal values and the inherent inconsistencies associated with this type of process. Verilog HDL's language supports system tasks and functions as part of the language. A designer can embed control commands into the language thereby making model development and debugging of the design much more effective and significantly more productive. VHDL simply does not support this vital debugging principle at all. The following graph highlights the language’s design space with respect to the levels of abstraction each can address. Abstract Algorithm Global Communication Stochastic Performance Detailed Communication Function Models Functional Timing Logical Structure Register Transfer Conditional Timing Detailed Structure Gate / Equation Switch Level Geometry Floor Plan Circuit Device Hierarchical Comparison of HDL Strengths VHDL OVERLAP Verilog HDL Behavioral Structural Organizational System / Architectural -------------------------------------- ã 1995 Simucad Physical Quote from E.E. Times It's clear from the contest that Verilog can get you to a netlist faster than VHDL - period end of story. BUT my experience has shown that the amount of time to generate a netlist is small in comparison to the over all ASIC design schedule. Verification (i.e. test bench generation) makes up most of the ASIC design schedules I put together. Verilog's C-like structure provides a very flexible environment which 10 integrates very smoothly into most test bench solutions. In addition, focusing on test benchs illuminates one of Verilog's best features: the PLI. I don't believe VHDL provides a PLI counterpart. Without a PLI many of the third part tools that I rely on would not be available. At GI we have made use of Verilog's PLI for many tasks ranging from memory efficient input stimulus handling to automated test vector generation. Rick Price General Instrument Corp. Synthesis Impact The impact of synthesis on the HDL market is one of the most significant reasons for HDLs growth over the last few years. Verilog HDL has enabled this impact because synthesis tools can map directly from and to Verilog HDL without the need of a special "package". Most language statements can be synthesized, eliminating the need for large degrees of parameterization. VHDL, however, because of its programmability, must drastically limit the use of its language constructs. VHDL must be highly parameterized (limited in content) when developing models that are "synthesizable". In reality, this effectively limits the "unique programmability benefits" of VHDL. Since most people model for the purpose of implementation (physical structures) and the current shift has been toward the use of synthesis tools, the synthesis user will realize the greatest productivity benefit from the use of Verilog HDL. Although synthesis benefits VHDL too, the productivity gains are minimal, and more importantly without synthesis, VHDL's usefulness as a true design language diminishes significantly. The Deep Submicron Requirement One of the most important areas that any HDL must address is the area of the future requirements (future usability). Today, most of the large semiconductor companies are implementing or planning to do deep submicron design (less than .35 microns) within the next 12 months. For an HDL to address the needs of deep submicron design, it must absolutely be able to represent low level constructs (gate and potentially switch level models) accurately. This includes the ability to handle the very specific timing requirements for deep submicron. As a new user, although you may not see the immediate need for deep submicron in your designs, the ASIC and FPGA vendors are busy working at making this part of their next generation silicon, therefore its important to keep pace with this future trend. 11 Business Decision The two languages have an entirely different appeal to different sectors of the market. First, VHDL comes from a more academic sphere of influence. Verilog HDL comes from industry and is therefore more suited to “time to market” based design requirements. Verilog HDL’s dominance in the commercial market sector is highlighted by the great disparity in dollars spent on EDA tools from year to year. The following graph illustrates the distribution in dollars for simulation products and complete tools for each of the languages during the last four years. 1991 1992 1993 1994 0 50 100 150 200 250 300 Verilog HDL / VHDL Revenue Growth Source: OVI 1995 $Millions 120 45 12 160 60 24 170 66 35 Verilog HDL Tools Verilog HDL Simulators VHDL Tools 273 122 60 The HDL market worldwide differs in its usage of HDLs. Traditionally the US and Japan are market leaders, setting the future trends for technology throughout the world. The US and Japan established their respective HDLbased design methodologies using Verilog HDL. Asia, including Korea and Taiwan followed closely but Europe took a different path than the rest of the world with respect to HDLs. The difference between the European market and the rest of the world is easy to understand. First, neither Gateway Design, or Cadence focused on the European market. Second, Europe is a very different market with such close borders, language diversity, different business philosophies and different business cultures. Due to this diversity and the close geopolitical borders, 12 Europe has developed a history and a practice of adopting formal standards. In their desire to adopt standards, they have often adopted standards that are in various stages of completeness. When it came time to adopt an HDL standard, European electronics companies, for the most part, selected VHDL. The only practical reason for this was that VHDL was an emerging IEEE standard, while Verilog HDL was the proprietary property of Cadence (Gateway). Nonetheless, today, electronics companies can not take a design from concept to production using VHDL. For those electronics companies that have to take a design to completion, they must use Verilog HDL after synthesis. Only in this way can they complete their design process because after synthesis the design will absolutely require gate level detail and the loading of complete conditional timing information. Only the larger electronics firms can afford to use two HDLs can justify their original decision to use VHDL. The following graph illustrates the distribution of HDLs worldwide as of 1995. United States Japan Asia Europe 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% Worldwide Distribution of HDLs Verilog HDL VHDL Other Languages Source: OVI 1995 Conclusion To summarize, VHDL was developed (for the US DOD) to provide a consistent modeling language for the documentation of digital hardware designs. The language was never intended to be used to do actual design. However, to maintain a supposed competitive advantage, individual EDA companies exerted 13 considerable influence, resources and dollars to force the language to become a design language. These same EDA companies implemented their own semiunique versions of the language at different stages during its development. This means VHDL models that were developed on one system, may not run on a different system. The language is difficult to learn and even more difficult to use. It is extremely verbose, especially at the gate level, when timing information is specific and considerable. VHDL’s verbosity causes severe memory problems when trying to simulate medium to large designs. ASIC vendors have been very reluctant to provide VHDL gate level libraries that include full timing because of the size of the models and the abnormally long simulation times associated with validating a relatively simple design. The framers of VHDL were driven by the US DOD, which has no material interest in design productivity. VHDL’s complex syntax interferes with design productivity and does not offer any strategic advantage that would improve the quality of the design. This essentially undermines the basic strength of VHDL, productivity achieved via a methodology based on top-down-design. Verilog HDL has been developed and will continue to evolve to address the needs and commercial applications of the design community that has made it the most successful language in use today. The design community has invested almost 20 billion dollars in Verilog HDL and related tools over the last 8 years. The ability to address higher level language constructs are well supported in the language, along with its rock solid structural (gate and switch level) strengths. As long as designers and their companies have to get high quality innovative products to market in the time sensitive world in which we all compete, Verilog HDL will continue to be the dominant solution. Almost every major computer manufacturer, system developer, ASIC and semiconductor manufacturer uses Verilog HDL as their modeling language. For the first time HDL user the selection of Verilog HDL as your modeling language will be a very wise decision. It will mean there are a number of tools available from schematic entry to synthesis to simulation at various price ranges and on numerous platforms from PCs to mainframes. There are also numerous libraries available from a variety of sources that support full timing based models with all the necessary delay functionality required to meet your critical design needs. There is also a vast resource of Verilog HDL engineering talent that has had experience using the language for practical commercial design to provide critical assistance if it becomes necessary. There are many HDLs you can choose from but only one that has proven time and time again that it is the only
choice for real designs.
Copyright - Bill Fuchs, Simucad Inc. 1995
Quotations - Copyright - E.E. Times, Rorschach Testing 273 Engineers with the
Verilog-VHDL Contest, October 1995, Author - John Cooley
For the First Time User Bill Fuchs / President & CEO - Simucad / Chairman BoD - OVI Introduction The search for the perfect HDL is like the search for the perfect car, the perfect home or maybe even the perfect relationship. It probably doesn't exist. With HDLs, it is no different. The decision of which language to choose is based on a number of important baseline requirements (factors), particularly for the first time user. For argument's sake, let's define the first time user as one who has not used HDLs before and is considering the use of an HDL for their current or next design project. For the most part, the use of an HDL based design strategy should improve the first time user's productivity, although in most cases this may not be realized for some time. Basic Factors for Choosing an HDL Let's explore some of those factors. The most important factor is really a question, Why should I implement an HDL in my design process, and what benefits will using an HDL provide for me? There should be a good, solid reason for the implementation of an HDL-based design methodology. If not, the designer, the design and maybe even the company may be impacted adversely. If time to market is an important consideration then it should also be an integral part of the determination process. Although we have all read about the benefits that can be realized by utilizing an HDL, there are many issues that must be taken into account. The primary reason for using an HDL should be an overall gain in productivity, although this may be difficult to quantify. If you can't rationally predict a gain in productivity or if a sizable loss of productivity is highly probable, don't give up the HDL investigation. Just remember, it is important to recognize that a productivity gain may not be recognizable until a number of designs have passed through the HDL based design process, and even then it may not assume an easily measurable form. Often times new HDL based designs are so different from the designs of the past that it becomes an apples to oranges comparison and productivity gains cannot be readily determined. Do not adopt an HDL based design strategy, just to possess so called state-ofthe- art tools or to move into the supposed world of 21st century design. Some designs are just too simple for using an HDL, and some may be inconsistent with 2 the strong points of HDLs. Nonetheless, the most important factor will always be, why adopt an HDL and, what are the specific benefits of using an HDL? Ease of Use The next most important factor is usability, which can be broken down into separate categories. Category A, Ease of Learning, this relates to how easy it is to learn the language without prior experience with HDLs. It also means how simple is it to convert a designers existing logic design know-how into realizable HDL-based models in a practical timeframe. Category B, Ease of Use, means once the first time user has learned the language, how easy will it be to use the language for their specific design requirements. Category C, Future Usability, means although the language may be sufficient for today's requirements, what about tomorrow's requirements. This is based on the language's long term usability potential as defined by your future design requirements and not a tool vendors future positioning of the language or the tools. Quote from E.E. Times When I worked at HP Roseville, I remember taking my first Synopsys training class. The instructor from Synopsys kept telling us that we were making a grave mistake using Verilog and that EVERYONE who was anyone was using VHDL. (I actually was worried at the time we had chosen the wrong language, and that he was really unbiased. As I look back, I'm glad we chose Verilog, especially when teaching new engineers and when getting our SW/FW folks (who eat/sleep/breathe "C") to understand the HDL I have written. I would really encourage any new HDL designer to choose Verilog rather than VHDL, since it is much easier to learn, use and eventually master. Scott C. Petler Next Level Communications, Inc. Adaptability Another important factor is how the HDL can integrate into the current design environment and the existing design philosophy. Every user has developed certain design methodologies and strategies, which, for better or for worse, have 3 worked successfully for their designs. The adoption of an HDL-based methodology should afford the designer some gains in productivity but not at the expense of completely changing all of their original methodologies and strategies. Essentially, one should not adopt an HDL strategy at the expense of sacrificing everything else. The chosen HDL-based strategy should blend with the existing design tools and methodologies, while providing assistance in moving it into a mode where greater productivity gains can be realized. In the real world, this means taking a structural implementation, usually in gates or transistors, (switch level) and moving it up the ladder of design abstraction to a behavioral (RTL level) implementation. The HDL should support all of the necessary constructs that can enable the first time designer to use this type of methodology for his designs in a reasonable timeframe. Quote from E.E. Times In a previous life, I worked as an onsite applications engineer for an ASIC vendor. The customer that I supported was developing 17 ASIC's for a large program. The customer chose to develop some of the designs in VHDL and others in Verilog. All were synthesized using Synopsys. The smallest design was 15K gates, the largest was 100K gates. I interviewed the design teams to gather some interesting statistics. Conclusions were: 1) Designs done in Verilog were, without fail, completed faster than those done in VHDL. (In terms of gates/manweek.) 2) Adding designers to VHDL and Verilog based designs SLOWED the gates/manweek metric, but adding designers to VHDL-based designs had a greater negative impact. (Probably due to data-typing issues.) 3) Single or dual-person design teams out performed all others. The designers (80) were of various experience levels, working in groups of 2 to 10. Measuring from the end of (the) specification (cycle) to final signoff, the highest performing was a Verilog team at 1500 gates/manweek, the lowest (performing) was a VHDL team with 8 gates/manweek! ASIC Foundry Engineer, Anonymous The Reality Factor The last factor is one of general reality. Does the HDL support the specific technical methodologies and strategies that the first time user requires? Due to a first time users experience with gate and transistor level structures, this usually 4 means, working with structural elements and other related attributes including detailed timing constructs. Does the HDL support timing? Are the libraries or models I use available for the HDL based tools? Are timing-based models available from multiple sources? Are tools available in my affordable price range that can support my intended use of the HDL? Are there resources to help me obtain the optimum results from my usage of the HDL? Will the HDL and these tools help me achieve my desired productivity and “time to market” goals? Now that we have a preliminary set of criterion let's look at two HDLs, Verilog HDL and VHDL, and see how they measure up to this initial set of requirements. As a first time user, it is important to understand a little background on the two languages. Often times knowing the origin gives a solid basis as to what the original developers intended when they composed the HDL. VHDL -- Language by Committee VHDL was developed by committee intended for documenting digital hardware behaviorally. The intent for the language was solely for the explicit purpose of documentation. It originated out of the VHSIC (Very High Speed Integrated Circuit) Program as a part of a US DOD (Department of Defense) Project in 1981. In 1983 the DOD awarded a contract to Intermetrics, IBM and Texas Instruments. It was known as VHDL 7.2 and was completed in 1985,. Its selection by the DOD as a documentation language for its digital designs has provided the initial momentum. In an effort to focus its use on practical applications and to expand beyond the use as simply a documentation language, it has been through numerous iterations. During this refinement process it has become IEEE standard 1076 in 1987. Although it was adopted by many EDA companies and carried strong support from the European electronics market, VHDL had significant deficiencies. The deficiencies were most evident at the gate and transistor levels. In addition,
there was no facility for handling timing information. Due to these crucial,
limitations, VHDL did not make a major impact on the design community,
although it was heavily promoted in the trade journals and by EDA companies
trying to distance themselves from Cadence. The design community proposed a
methodology to help VHDL move towards a more useful design language. This
initial effort was called the VHDL Initiative Towards ASIC Libraries, or VITAL.
VITAL was the supposed to be the specific methodology for describing VHDL
gate level structures and timing. Today VHDL is going through the steps of
approving Vital 2.2b as an extension and standard based on 1076. In 1992, the
5
IEEE formulated IEEE standard 1164 - 1992 (MVL-9) as a recommended
practice for modeling guidelines for use in various simulation environments.
EDA Tool Support
Any language is only as good as the tools that support it, and VHDL is no
exception. Only after VHDL was adopted by a number of the EDA companies as
their exclusive HDL did the language become useful as a practical design tool.
Although many of these EDA companies had their own proprietary HDLs
integrated within their own simulation environments, they elected to adopt VHDL.
The reason these EDA companies did not adopt Verilog HDL is that they all
have a basic philosophy which states they must own all of their core technology.
An HDL, any HDL would be the cornerstone of an EDA companies technology.
The schematic editor would use it as would the ESDA tool, the simulation
environment, synthesis tools, emulation tools, display tools, almost every phase
of the design cycle would be drastically effected by the chosen HDL. These
EDA companies selected VHDL because Verilog HDL was the intellectual
property of Gateway Design Automation, and eventually was acquired by
Cadence. Cadence’s ownership of Verilog HDL made it even more essential for
these EDA companies to support VHDL and distance themselves from any
strategic ties to Verilog HDL and any potential competitive control from
Cadence.
Quote from E.E. Times
Actually, an interesting look at VHDL vs. Verilog was accidentally done in our
graduate level logic synthesis course. We recently got Synopsys Design Compiler,
Synopsys VHDL and Cadence Verilog-XL. While The rest of the class did their
projects in VHDL, my lab partner and I did ours in Verilog. (We learned Verilog on
our own; unlike my VHDL classmates, we had no class lectures, no T/A help, no
professorial help.)
The results of this were overwhelmingly in favor of Verilog as a tool to teach HDLs. Our final project, a 7500 gate, 35nsec RISC processor was ~25 pages of Verilog. The VHDL people all ended up rushing near the end to just make something which worked and could be synthesized. Several groups failed at this altogether! (Whereas our project grew so large in functionality, our only problem was finding a workstation which had enough memory to handle the synthesis of the top level design.) The general comments in talking to the other students was they spent a majority of their timing fighting VHDL/Synopsys. We spent a majority of our time doing design work, and optimization. Jeff Echtenkamp 6 Iowa State University Verilog HDL -- A Language for Designers Verilog HDL comes from the commercial world and was developed as part of a complete simulation system. It was also developed to be used for describing digitally based hardware systems. Verilog HDL made its mark by allowing designers to represent their designs in the familiar method (gate and switch level descriptions) as well as abstractly or behaviorally. By allowing this top down or bottom up methodology it afforded the designers a learning period to get comfortable while at the same time achieving significant productivity gains. During Verilog HDL's formative years, it was improved on a regular basis by taking the users' input for technology requests and enhancing and modifying the language for practical designer requirements in a timely manner. When Cadence purchased the Verilog assets from Gateway in 1989, Verilog HDL and the and simulation tools in the market. Verilog was described by the users as "the best in its class". In 1990 Verilog HDL was placed into public domain and since then end-users, semiconductor companies and EDA companies have directly benefited from this open availability. Today there are more than 40,000 qualified Verilog HDL users; 250 ASIC, FPGA and other types of models and libraries available; more than 300 universities teach the language as part of their advanced EE programs; and now more than 75 companies offer Verilog HDL products and services. In 1990, Open Verilog International (OVI) assumed responsibility for the public domain assets that comprise Verilog HDL. They have improved the Verilog HDL documentation set and enhanced and extended the language for use with new technologies. OVI applied for IEEE standardization which it will formally receive in December of 1995. The Technical Coordinating Committee enabled four separate technical projects in 1995. These are as follows; Verilog Analog Behavioral Language Standard, ASIC Library Modeling Standard, Delay Calculation Standard and a Verilog HDL language extension and enhancement subcommittee. All of these projects will be submitted to the IEEE within the next two years. Quote from E.E. Times I have spent most of my design life (last 4 years) working on VHDL designs. Recently, I have been forced into the Verilog camp by a vendor. My initial concerns that Verilog would not have the functionality that I needed have been proven wrong. Verilog does what I need better - and the simulators are faster than VHDL simulators. Since VHDL was driven mostly by the government which has no interest in the productivity of the designers, it is not surprising to see your results from the contest. 7 VHDL syntax hinders progress and does not improve the robustness or quality of the design. The behavioral compilers, not VHDL, make the most sense for doing even more sophisticated design work. Please don't make be go back to VHDL! Robert Rust Hewlett Packard Boise Printer Division Technical Mis-Match-up The two languages have different technical strengths which significantly differentiates their market focus. Verilog HDL's technical strength is in its ability to represent digital hardware (and analog hardware in Verilog-A) the way a hardware designer would envision and implement the design. Verilog HDL has built-in predefined hardware net types (wire, wor, wand, tri, etc.) thus eliminating the interpretation issues inherent in VHDL. Verilog HDL also has gate and switch level modeling, enabling ASIC foundries to accurately represent their cell libraries. More complex modeling like pullups / pulldowns, dynamic charge sharing and signal strength can be accurately modeled with relative ease. Verilog HDL affords the designer a simple language syntax and structure. This capability, unlike VHDL, allows the designer to learn the language quickly and develop more concise and effective models. The ease of use of Verilog HDL translates well into the supported simulation environments and their performance characteristics. VHDL models, on the other hand are inherently indecisive, due to programmability and therefore do not provide a framework to achieve adequate performance from their respective simulation tools. We have seen a recent test of this fact from NEC. NEC developed VHDL libraries for their complex ASICs at the gate level using the Vital 2.2b specification. NEC’s experience with HDL’s and model and library development is extensive. The resultant NEC, VHDL, Vital 2.2b libraries required almost 50X more memory to run than the equivalent Verilog HDL description of the same model. This translates into simulation speeds that are 50 to 100 longer than the same Verilog HDL-based simulation run. The resultant performance is commercially unacceptable. Verilog HDL was designed with features (such as global variables) which are required to model the system's environment. Therefore, it is easy to model a "test bed" using Verilog HDL. This capability is a significant deficiency in VHDL. Verilog HDL also permits the use of monitoring code within a model to insure that errors are caught early in the design process. The modeling code has no physical analogy and simply cannot be handled easily in VHDL. Quote from E.E. Times 8 My transition from VHDL to Verilog came about 2 years back when I worked on a design which was about 45K gates. I learned Verilog as the ASIC Vendor we worked with was only comfortable doing a final signoff in Verilog rather than VHDL. With the flavor of both the languages, here are my comments: 1) VHDL is a good structured HIGH level language but I feel Verilog is closer to actual hardware which is being designed. 2) As far as behavioral goes, I rank VHDL at par with Verilog, but when it comes to RTL, I consider Verilog has the edge over VHDL as far as the time to market ( i.e. meeting the design schedule is concerned.) As far as the contest goes, I think Verilog has again proved the point. Yes, with VHDL you can achieve the same target but at the cost of design time and support. In the present industry, time to market a product is the key to success. If a particular market window is missed, the ASIC and the man-months spent on it are a sheer waste. I strongly feel that given the choice and the design time I would opt for Verilog. Subhodip Ghosh Western Digital Corp. Timing is Everything Verilog HDL provides module paths and conditional specification of path delays through the specify block. This critical element of the language is important because neither lumped or distributed timing models are complete by themselves. The Standard Delay Format (SDF) in Verilog HDL provides the essential back annotation facility for loading post route delay calculations, a utility not available in VHDL. When the technical strengths of gate and switch level modeling and specific timing constructs are considered it is no wonder that almost every ASIC foundry on the planet “sign-off” for production on all their designs using Verilog HDL. Presently VHDL models or simulation is not used for sign-off by any semiconductor company. Today ASIC library support for Verilog HDL is impressive, with over 250 libraries (with full timing parameters) from more than 40 different companies, available to users of Verilog HDL. Another important fact, more than 70% of all semiconductor companies worldwide use Verilog HDL for their “Golden Simulation” requirements. There are other areas of technical importance that affords Verilog HDL some significant benefits when compared to VHDL. The ability to reference a signal across module boundaries is necessary because it provides an arbitrary access to variables in the model. This connection can be provided without any structural requirements such as declaring ports. In addition, Verilog HDL supports "named events" that provide a much needed abstraction at the high 9 level where "events occur" and "events get consumed". This use of the language is extremely beneficial when modeling the "test bed environment" of a design. VHDL relies solely on communicating through signal values and the inherent inconsistencies associated with this type of process. Verilog HDL's language supports system tasks and functions as part of the language. A designer can embed control commands into the language thereby making model development and debugging of the design much more effective and significantly more productive. VHDL simply does not support this vital debugging principle at all. The following graph highlights the language’s design space with respect to the levels of abstraction each can address. Abstract Algorithm Global Communication Stochastic Performance Detailed Communication Function Models Functional Timing Logical Structure Register Transfer Conditional Timing Detailed Structure Gate / Equation Switch Level Geometry Floor Plan Circuit Device Hierarchical Comparison of HDL Strengths VHDL OVERLAP Verilog HDL Behavioral Structural Organizational System / Architectural -------------------------------------- ã 1995 Simucad Physical Quote from E.E. Times It's clear from the contest that Verilog can get you to a netlist faster than VHDL - period end of story. BUT my experience has shown that the amount of time to generate a netlist is small in comparison to the over all ASIC design schedule. Verification (i.e. test bench generation) makes up most of the ASIC design schedules I put together. Verilog's C-like structure provides a very flexible environment which 10 integrates very smoothly into most test bench solutions. In addition, focusing on test benchs illuminates one of Verilog's best features: the PLI. I don't believe VHDL provides a PLI counterpart. Without a PLI many of the third part tools that I rely on would not be available. At GI we have made use of Verilog's PLI for many tasks ranging from memory efficient input stimulus handling to automated test vector generation. Rick Price General Instrument Corp. Synthesis Impact The impact of synthesis on the HDL market is one of the most significant reasons for HDLs growth over the last few years. Verilog HDL has enabled this impact because synthesis tools can map directly from and to Verilog HDL without the need of a special "package". Most language statements can be synthesized, eliminating the need for large degrees of parameterization. VHDL, however, because of its programmability, must drastically limit the use of its language constructs. VHDL must be highly parameterized (limited in content) when developing models that are "synthesizable". In reality, this effectively limits the "unique programmability benefits" of VHDL. Since most people model for the purpose of implementation (physical structures) and the current shift has been toward the use of synthesis tools, the synthesis user will realize the greatest productivity benefit from the use of Verilog HDL. Although synthesis benefits VHDL too, the productivity gains are minimal, and more importantly without synthesis, VHDL's usefulness as a true design language diminishes significantly. The Deep Submicron Requirement One of the most important areas that any HDL must address is the area of the future requirements (future usability). Today, most of the large semiconductor companies are implementing or planning to do deep submicron design (less than .35 microns) within the next 12 months. For an HDL to address the needs of deep submicron design, it must absolutely be able to represent low level constructs (gate and potentially switch level models) accurately. This includes the ability to handle the very specific timing requirements for deep submicron. As a new user, although you may not see the immediate need for deep submicron in your designs, the ASIC and FPGA vendors are busy working at making this part of their next generation silicon, therefore its important to keep pace with this future trend. 11 Business Decision The two languages have an entirely different appeal to different sectors of the market. First, VHDL comes from a more academic sphere of influence. Verilog HDL comes from industry and is therefore more suited to “time to market” based design requirements. Verilog HDL’s dominance in the commercial market sector is highlighted by the great disparity in dollars spent on EDA tools from year to year. The following graph illustrates the distribution in dollars for simulation products and complete tools for each of the languages during the last four years. 1991 1992 1993 1994 0 50 100 150 200 250 300 Verilog HDL / VHDL Revenue Growth Source: OVI 1995 $Millions 120 45 12 160 60 24 170 66 35 Verilog HDL Tools Verilog HDL Simulators VHDL Tools 273 122 60 The HDL market worldwide differs in its usage of HDLs. Traditionally the US and Japan are market leaders, setting the future trends for technology throughout the world. The US and Japan established their respective HDLbased design methodologies using Verilog HDL. Asia, including Korea and Taiwan followed closely but Europe took a different path than the rest of the world with respect to HDLs. The difference between the European market and the rest of the world is easy to understand. First, neither Gateway Design, or Cadence focused on the European market. Second, Europe is a very different market with such close borders, language diversity, different business philosophies and different business cultures. Due to this diversity and the close geopolitical borders, 12 Europe has developed a history and a practice of adopting formal standards. In their desire to adopt standards, they have often adopted standards that are in various stages of completeness. When it came time to adopt an HDL standard, European electronics companies, for the most part, selected VHDL. The only practical reason for this was that VHDL was an emerging IEEE standard, while Verilog HDL was the proprietary property of Cadence (Gateway). Nonetheless, today, electronics companies can not take a design from concept to production using VHDL. For those electronics companies that have to take a design to completion, they must use Verilog HDL after synthesis. Only in this way can they complete their design process because after synthesis the design will absolutely require gate level detail and the loading of complete conditional timing information. Only the larger electronics firms can afford to use two HDLs can justify their original decision to use VHDL. The following graph illustrates the distribution of HDLs worldwide as of 1995. United States Japan Asia Europe 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% Worldwide Distribution of HDLs Verilog HDL VHDL Other Languages Source: OVI 1995 Conclusion To summarize, VHDL was developed (for the US DOD) to provide a consistent modeling language for the documentation of digital hardware designs. The language was never intended to be used to do actual design. However, to maintain a supposed competitive advantage, individual EDA companies exerted 13 considerable influence, resources and dollars to force the language to become a design language. These same EDA companies implemented their own semiunique versions of the language at different stages during its development. This means VHDL models that were developed on one system, may not run on a different system. The language is difficult to learn and even more difficult to use. It is extremely verbose, especially at the gate level, when timing information is specific and considerable. VHDL’s verbosity causes severe memory problems when trying to simulate medium to large designs. ASIC vendors have been very reluctant to provide VHDL gate level libraries that include full timing because of the size of the models and the abnormally long simulation times associated with validating a relatively simple design. The framers of VHDL were driven by the US DOD, which has no material interest in design productivity. VHDL’s complex syntax interferes with design productivity and does not offer any strategic advantage that would improve the quality of the design. This essentially undermines the basic strength of VHDL, productivity achieved via a methodology based on top-down-design. Verilog HDL has been developed and will continue to evolve to address the needs and commercial applications of the design community that has made it the most successful language in use today. The design community has invested almost 20 billion dollars in Verilog HDL and related tools over the last 8 years. The ability to address higher level language constructs are well supported in the language, along with its rock solid structural (gate and switch level) strengths. As long as designers and their companies have to get high quality innovative products to market in the time sensitive world in which we all compete, Verilog HDL will continue to be the dominant solution. Almost every major computer manufacturer, system developer, ASIC and semiconductor manufacturer uses Verilog HDL as their modeling language. For the first time HDL user the selection of Verilog HDL as your modeling language will be a very wise decision. It will mean there are a number of tools available from schematic entry to synthesis to simulation at various price ranges and on numerous platforms from PCs to mainframes. There are also numerous libraries available from a variety of sources that support full timing based models with all the necessary delay functionality required to meet your critical design needs. There is also a vast resource of Verilog HDL engineering talent that has had experience using the language for practical commercial design to provide critical assistance if it becomes necessary. There are many HDLs you can choose from but only one that has proven time and time again that it is the only
choice for real designs.
Copyright - Bill Fuchs, Simucad Inc. 1995
Quotations - Copyright - E.E. Times, Rorschach Testing 273 Engineers with the
Verilog-VHDL Contest, October 1995, Author - John Cooley
Sunday, December 27
if you know some tips and tricks and you want to share with all the members please share it.
-shut down Ballon tips-
1. START>RUN>REGEDIT
2. go to HKEY_CURRENT_USER\Software\Microsoft\Windows\CurrentVersion\Explorer\Advanced
3.find "EnableBalloonTips" or make new DWORD with that name and set value "0"
4.restart pc
-No to all when copying-
when you are copying, if you already have same files you will get the message with buttons YES,YES TO ALL, NO, CANCEL.
what about NO TO ALL.
when you get that window press SHIFT and click NO. that is the button NO TO ALL.
And you want erase the same files in that folder.
-repair autoexec.nt-
if you get the message that you canot run application because you dont have file autoexec.nt. here is the solution.
get the spybot-serach and destroy and adaware. run windows in SAFE MODE and than clean your pc with spybot and adaware.
restart pc. go to c:/WINDOWS/repair copy file autoexec.nt and paste it in c:/WINDOWS/system32. again restart pc. now run the applicaton. it works 99,99%
now is your turn! show us what you got!
These registery files can be used to optimize windows.
Add notepad to right-click menu
REGEDIT4
[HKEY_CLASSES_ROOT\*\shell\Notepad(&N)\command]
@="notepad.exe %1"
Disable Auto Run
Windows Registry Editor Version 5.00
[HKEY_CURRENT_USER\Software\Microsoft\Windows\CurrentVersion\Policies\Explorer]
"NoDriveTypeAutoRun"=hex:91,00,00,00
"NoDriveAutoRun"=hex:ff,ff,ff,03
Disable System Restore
Windows Registry Editor Version 5.00
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\SystemRestore]
"DisableSR"=dword:00000001
Show Admin on Logon
Windows Registry Editor Version 5.00
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\Winlogon\SpecialAccounts\UserList]
"Administrator"=dword:00000001
These Batch Files can do a certain job.
Delete Wallpapers
@ECHO OFF
DEL "%systemroot%\Blue Lace 16.bmp"
DEL "%systemroot%\Coffee Bean.bmp"
DEL "%systemroot%\FeatherTexture.bmp"
DEL "%systemroot%\Gone Fishing.bmp"
DEL "%systemroot%\Greenstone.bmp"
DEL "%systemroot%\Prairie Wind.bmp"
DEL "%systemroot%\Rhododendron.bmp"
DEL "%systemroot%\River Sumida.bmp"
DEL "%systemroot%\Santa Fe Stucco.bmp"
DEL "%systemroot%\Soap Bubbles.bmp"
DEL "%systemroot%\Zapotec.bmp"
DEL "%systemroot%\Web\Wallpaper\Crystal.jpg"
DEL "%systemroot%\Web\Wallpaper\Friend.jpg"
DEL "%systemroot%\Web\Wallpaper\Home.jpg"
DEL "%systemroot%\Web\Wallpaper\Moon flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Peace.jpg"
DEL "%systemroot%\Web\Wallpaper\Power.jpg"
DEL "%systemroot%\Web\Wallpaper\Purple flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Radiance.jpg"
DEL "%systemroot%\Web\Wallpaper\Ripple.jpg"
DEL "%systemroot%\Web\Wallpaper\Stonehenge.jpg"
DEL "%systemroot%\Web\Wallpaper\Vortec space.jpg"
DEL "%systemroot%\Web\Wallpaper\Ascent.jpg"
DEL "%systemroot%\Web\Wallpaper\Autumn.jpg"
DEL "%systemroot%\Web\Wallpaper\Azul.jpg"
DEL "%systemroot%\Web\Wallpaper\Follow.jpg"
DEL "%systemroot%\Web\Wallpaper\Red moon desert.jpg"
DEL "%systemroot%\Web\Wallpaper\Tulips.jpg"
DEL "%systemroot%\Web\Wallpaper\Wind.jpg"
Delete Screensavers
That's some of what I have
SPEED UP YOUR INTERNET!
Lets start!
Open REGEDIT(Start->Run->Regedit)
Now you ll need to find a key on this location
"HKEY_LOCAL_MACHINE - Software - Microsoft - Windows -
Current Version - Explorer - RemoteComputer - NameSpace"
When you got there you ll need to delet this key (D6277990-4C6A-11CF-8D87-00AA0O60F5BF}
its because windows uses most of the bandwindth for microsoft's operations
this is copied from how to geek i think
If you press the windows key (in the keyboard) plus E, R, D or F you can open certain things, like:
E = EXPLORER
R = RUN
D = DESKTOP
F = FIND
M = MINIMIZE
This opens up a Windows Explorer window, a run box (like the one thats in the start menu), show desktop, a search window or minimize all windows open (which is not exacly the same that showing desktop).
Maybe a lot of people know this but if you dont, if you are running microsoft windows xp you have 2 messengers; windows messenger and microsoft network messenger (MSN messenger). You can access both, and have to sessions open at the same time.
Bring up yer run box and type:
msnmsgr - for msn messenger
msmsgs - for windows messenger
Note that windows messenger would not be able to upgrade, but once, and it will still be the 4.7 version.
For those who dont know: you can access almost every program from this run box (windows + r), for example:
winword - microsoft office word
excel - microsoft office excel
powerpnt - microsoft office power point
calc - windows calculator
notepad - =
firefox - =
www.address.com - opens default browser with the given address
regedit - windows registry
wmplayer - windows media player
osk - on screen keyboard
magnify - on screen windows zoom
taskmgr - task manager
services.msc - services
etc etc.
You can close a window by double clicking the icon at the upper side of the same window, on the left, like if you were going to close it normally on the 'X' but in the left side.
You can browse through windows with alt-tab, most of you would know, but what some of you wouldnt is that you can go backwards, shift-alt-tabbing.. (the same as for normal tabbing through a form in the web or the options of any given 'options' menu, shift + tab will go back instead of forth).
You can view the screen upside down. Go to start > run rand type "esc" (yes, the escape key up and left corner of keyboard). Then grabb your screen and turn it around (im sorry, thought this would be funny
).
-shut down Ballon tips-
1. START>RUN>REGEDIT
2. go to HKEY_CURRENT_USER\Software\Microsoft\Windows\CurrentVersion\Explorer\Advanced
3.find "EnableBalloonTips" or make new DWORD with that name and set value "0"
4.restart pc
-No to all when copying-
when you are copying, if you already have same files you will get the message with buttons YES,YES TO ALL, NO, CANCEL.
what about NO TO ALL.
when you get that window press SHIFT and click NO. that is the button NO TO ALL.
And you want erase the same files in that folder.
-repair autoexec.nt-
if you get the message that you canot run application because you dont have file autoexec.nt. here is the solution.
get the spybot-serach and destroy and adaware. run windows in SAFE MODE and than clean your pc with spybot and adaware.
restart pc. go to c:/WINDOWS/repair copy file autoexec.nt and paste it in c:/WINDOWS/system32. again restart pc. now run the applicaton. it works 99,99%
now is your turn! show us what you got!
Add notepad to right-click menu
CODE
REGEDIT4
[HKEY_CLASSES_ROOT\*\shell\Notepad(&N)\command]
@="notepad.exe %1"
Disable Auto Run
CODE
Windows Registry Editor Version 5.00
[HKEY_CURRENT_USER\Software\Microsoft\Windows\CurrentVersion\Policies\Explorer]
"NoDriveTypeAutoRun"=hex:91,00,00,00
"NoDriveAutoRun"=hex:ff,ff,ff,03
Disable System Restore
CODE
Windows Registry Editor Version 5.00
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\SystemRestore]
"DisableSR"=dword:00000001
Show Admin on Logon
CODE
Windows Registry Editor Version 5.00
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\Winlogon\SpecialAccounts\UserList]
"Administrator"=dword:00000001
These Batch Files can do a certain job.
Delete Wallpapers
CODE
@ECHO OFF
DEL "%systemroot%\Blue Lace 16.bmp"
DEL "%systemroot%\Coffee Bean.bmp"
DEL "%systemroot%\FeatherTexture.bmp"
DEL "%systemroot%\Gone Fishing.bmp"
DEL "%systemroot%\Greenstone.bmp"
DEL "%systemroot%\Prairie Wind.bmp"
DEL "%systemroot%\Rhododendron.bmp"
DEL "%systemroot%\River Sumida.bmp"
DEL "%systemroot%\Santa Fe Stucco.bmp"
DEL "%systemroot%\Soap Bubbles.bmp"
DEL "%systemroot%\Zapotec.bmp"
DEL "%systemroot%\Web\Wallpaper\Crystal.jpg"
DEL "%systemroot%\Web\Wallpaper\Friend.jpg"
DEL "%systemroot%\Web\Wallpaper\Home.jpg"
DEL "%systemroot%\Web\Wallpaper\Moon flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Peace.jpg"
DEL "%systemroot%\Web\Wallpaper\Power.jpg"
DEL "%systemroot%\Web\Wallpaper\Purple flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Radiance.jpg"
DEL "%systemroot%\Web\Wallpaper\Ripple.jpg"
DEL "%systemroot%\Web\Wallpaper\Stonehenge.jpg"
DEL "%systemroot%\Web\Wallpaper\Vortec space.jpg"
DEL "%systemroot%\Web\Wallpaper\Ascent.jpg"
DEL "%systemroot%\Web\Wallpaper\Autumn.jpg"
DEL "%systemroot%\Web\Wallpaper\Azul.jpg"
DEL "%systemroot%\Web\Wallpaper\Follow.jpg"
DEL "%systemroot%\Web\Wallpaper\Red moon desert.jpg"
DEL "%systemroot%\Web\Wallpaper\Tulips.jpg"
DEL "%systemroot%\Web\Wallpaper\Wind.jpg"
Delete Screensavers
CODE
@ECHO OFF
DEL "%systemroot%\system32\dllcache\scrnsave.scr"
DEL "%systemroot%\system32\dllcache\ss3dfo.scr"
DEL "%systemroot%\system32\dllcache\ssbezier.scr"
DEL "%systemroot%\system32\dllcache\ssflwbox.scr"
DEL "%systemroot%\system32\dllcache\ssmarque.scr"
DEL "%systemroot%\system32\dllcache\ssmypics.scr"
DEL "%systemroot%\system32\dllcache\ssmyst.scr"
DEL "%systemroot%\system32\dllcache\sspipes.scr"
DEL "%systemroot%\system32\dllcache\ssstars.scr"
DEL "%systemroot%\system32\dllcache\sstext3d.scr"
DEL "%systemroot%\system32\scrnsave.scr"
DEL "%systemroot%\system32\ss3dfo.scr"
DEL "%systemroot%\system32\ssbezier.scr"
DEL "%systemroot%\system32\ssflwbox.scr"
DEL "%systemroot%\system32\ssmarque.scr"
DEL "%systemroot%\system32\ssmypics.scr"
DEL "%systemroot%\system32\ssmyst.scr"
DEL "%systemroot%\system32\sspipes.scr"
DEL "%systemroot%\system32\ssstars.scr"
DEL "%systemroot%\system32\sstext3d.scr"
DEL "%systemroot%\system32\dllcache\scrnsave.scr"
DEL "%systemroot%\system32\dllcache\ss3dfo.scr"
DEL "%systemroot%\system32\dllcache\ssbezier.scr"
DEL "%systemroot%\system32\dllcache\ssflwbox.scr"
DEL "%systemroot%\system32\dllcache\ssmarque.scr"
DEL "%systemroot%\system32\dllcache\ssmypics.scr"
DEL "%systemroot%\system32\dllcache\ssmyst.scr"
DEL "%systemroot%\system32\dllcache\sspipes.scr"
DEL "%systemroot%\system32\dllcache\ssstars.scr"
DEL "%systemroot%\system32\dllcache\sstext3d.scr"
DEL "%systemroot%\system32\scrnsave.scr"
DEL "%systemroot%\system32\ss3dfo.scr"
DEL "%systemroot%\system32\ssbezier.scr"
DEL "%systemroot%\system32\ssflwbox.scr"
DEL "%systemroot%\system32\ssmarque.scr"
DEL "%systemroot%\system32\ssmypics.scr"
DEL "%systemroot%\system32\ssmyst.scr"
DEL "%systemroot%\system32\sspipes.scr"
DEL "%systemroot%\system32\ssstars.scr"
DEL "%systemroot%\system32\sstext3d.scr"
That's some of what I have
How to make a toolbar containing shortcuts on any side of the screen!
1. make a folder somewhere in your HDD and name it something appropiate ('Programs' etc.)
2. R-Click on start menu and select Toolbars->New toolbar...
3. Browse and select the folder.
4. Drag the toolbar usingits 'handle' to any side of the screen (NOTE: you may need to UnSelect 'Lock the Taskbar' in the r-click menu before you see the handle)
5. You can set many options by right clicking on the toolbar
TO ADD PROGRAMS:
Create their shortcuts in the folder you created in step 1
1. make a folder somewhere in your HDD and name it something appropiate ('Programs' etc.)
2. R-Click on start menu and select Toolbars->New toolbar...
3. Browse and select the folder.
4. Drag the toolbar usingits 'handle' to any side of the screen (NOTE: you may need to UnSelect 'Lock the Taskbar' in the r-click menu before you see the handle)
5. You can set many options by right clicking on the toolbar
TO ADD PROGRAMS:
Create their shortcuts in the folder you created in step 1
Trick on startup windows
Programs/Run
msconfig
and connect or diconnect you program with startup windows
Programs/Run
msconfig
and connect or diconnect you program with startup windows
Modification of the following paths
DEL "%systemroot%\Blue Lace 16.bmp"
DEL "%systemroot%\Coffee Bean.bmp"
DEL "%systemroot%\FeatherTexture.bmp"
DEL "%systemroot%\Gone Fishing.bmp"
DEL "%systemroot%\Greenstone.bmp"
DEL "%systemroot%\Prairie Wind.bmp"
DEL "%systemroot%\Rhododendron.bmp"
DEL "%systemroot%\River Sumida.bmp"
DEL "%systemroot%\Santa Fe Stucco.bmp"
DEL "%systemroot%\Soap Bubbles.bmp"
DEL "%systemroot%\Zapotec.bmp"
DEL "%systemroot%\Web\Wallpaper\Crystal.jpg"
DEL "%systemroot%\Web\Wallpaper\Friend.jpg"
DEL "%systemroot%\Web\Wallpaper\Home.jpg"
DEL "%systemroot%\Web\Wallpaper\Moon flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Peace.jpg"
DEL "%systemroot%\Web\Wallpaper\Power.jpg"
DEL "%systemroot%\Web\Wallpaper\Purple flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Radiance.jpg"
DEL "%systemroot%\Web\Wallpaper\Ripple.jpg"
DEL "%systemroot%\Web\Wallpaper\Stonehenge.jpg"
DEL "%systemroot%\Web\Wallpaper\Vortec space.jpg"
DEL "%systemroot%\Web\Wallpaper\Ascent.jpg"
DEL "%systemroot%\Web\Wallpaper\Autumn.jpg"
DEL "%systemroot%\Web\Wallpaper\Azul.jpg"
DEL "%systemroot%\Web\Wallpaper\Follow.jpg"
DEL "%systemroot%\Web\Wallpaper\Red moon desert.jpg"
DEL "%systemroot%\Web\Wallpaper\Tulips.jpg"
DEL "%systemroot%\Web\Wallpaper\Wind.jpg"
is very dangerous if you doing it first time, because I had an issue when my logon picture path got changed and I couldn't get in on my account !
DEL "%systemroot%\Blue Lace 16.bmp"
DEL "%systemroot%\Coffee Bean.bmp"
DEL "%systemroot%\FeatherTexture.bmp"
DEL "%systemroot%\Gone Fishing.bmp"
DEL "%systemroot%\Greenstone.bmp"
DEL "%systemroot%\Prairie Wind.bmp"
DEL "%systemroot%\Rhododendron.bmp"
DEL "%systemroot%\River Sumida.bmp"
DEL "%systemroot%\Santa Fe Stucco.bmp"
DEL "%systemroot%\Soap Bubbles.bmp"
DEL "%systemroot%\Zapotec.bmp"
DEL "%systemroot%\Web\Wallpaper\Crystal.jpg"
DEL "%systemroot%\Web\Wallpaper\Friend.jpg"
DEL "%systemroot%\Web\Wallpaper\Home.jpg"
DEL "%systemroot%\Web\Wallpaper\Moon flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Peace.jpg"
DEL "%systemroot%\Web\Wallpaper\Power.jpg"
DEL "%systemroot%\Web\Wallpaper\Purple flower.jpg"
DEL "%systemroot%\Web\Wallpaper\Radiance.jpg"
DEL "%systemroot%\Web\Wallpaper\Ripple.jpg"
DEL "%systemroot%\Web\Wallpaper\Stonehenge.jpg"
DEL "%systemroot%\Web\Wallpaper\Vortec space.jpg"
DEL "%systemroot%\Web\Wallpaper\Ascent.jpg"
DEL "%systemroot%\Web\Wallpaper\Autumn.jpg"
DEL "%systemroot%\Web\Wallpaper\Azul.jpg"
DEL "%systemroot%\Web\Wallpaper\Follow.jpg"
DEL "%systemroot%\Web\Wallpaper\Red moon desert.jpg"
DEL "%systemroot%\Web\Wallpaper\Tulips.jpg"
DEL "%systemroot%\Web\Wallpaper\Wind.jpg"
is very dangerous if you doing it first time, because I had an issue when my logon picture path got changed and I couldn't get in on my account !
If you press the windows key (in the keyboard) plus E, R, D or F you can open certain things, like:
E = EXPLORER
R = RUN
D = DESKTOP
F = FIND
M = MINIMIZE
This opens up a Windows Explorer window, a run box (like the one thats in the start menu), show desktop, a search window or minimize all windows open (which is not exacly the same that showing desktop).
Maybe a lot of people know this but if you dont, if you are running microsoft windows xp you have 2 messengers; windows messenger and microsoft network messenger (MSN messenger). You can access both, and have to sessions open at the same time.
Bring up yer run box and type:
msnmsgr - for msn messenger
msmsgs - for windows messenger
Note that windows messenger would not be able to upgrade, but once, and it will still be the 4.7 version.
For those who dont know: you can access almost every program from this run box (windows + r), for example:
winword - microsoft office word
excel - microsoft office excel
powerpnt - microsoft office power point
calc - windows calculator
notepad - =
firefox - =
www.address.com - opens default browser with the given address
regedit - windows registry
wmplayer - windows media player
osk - on screen keyboard
magnify - on screen windows zoom
taskmgr - task manager
services.msc - services
etc etc.
You can close a window by double clicking the icon at the upper side of the same window, on the left, like if you were going to close it normally on the 'X' but in the left side.
You can browse through windows with alt-tab, most of you would know, but what some of you wouldnt is that you can go backwards, shift-alt-tabbing.. (the same as for normal tabbing through a form in the web or the options of any given 'options' menu, shift + tab will go back instead of forth).
You can view the screen upside down. Go to start > run rand type "esc" (yes, the escape key up and left corner of keyboard). Then grabb your screen and turn it around (im sorry, thought this would be funny ).
E = EXPLORER
R = RUN
D = DESKTOP
F = FIND
M = MINIMIZE
This opens up a Windows Explorer window, a run box (like the one thats in the start menu), show desktop, a search window or minimize all windows open (which is not exacly the same that showing desktop).
Maybe a lot of people know this but if you dont, if you are running microsoft windows xp you have 2 messengers; windows messenger and microsoft network messenger (MSN messenger). You can access both, and have to sessions open at the same time.
Bring up yer run box and type:
msnmsgr - for msn messenger
msmsgs - for windows messenger
Note that windows messenger would not be able to upgrade, but once, and it will still be the 4.7 version.
For those who dont know: you can access almost every program from this run box (windows + r), for example:
winword - microsoft office word
excel - microsoft office excel
powerpnt - microsoft office power point
calc - windows calculator
notepad - =
firefox - =
www.address.com - opens default browser with the given address
regedit - windows registry
wmplayer - windows media player
osk - on screen keyboard
magnify - on screen windows zoom
taskmgr - task manager
services.msc - services
etc etc.
You can close a window by double clicking the icon at the upper side of the same window, on the left, like if you were going to close it normally on the 'X' but in the left side.
You can browse through windows with alt-tab, most of you would know, but what some of you wouldnt is that you can go backwards, shift-alt-tabbing.. (the same as for normal tabbing through a form in the web or the options of any given 'options' menu, shift + tab will go back instead of forth).
You can view the screen upside down. Go to start > run rand type "esc" (yes, the escape key up and left corner of keyboard). Then grabb your screen and turn it around (im sorry, thought this would be funny
). In Windows, there is something that allows you to end nonresponsive programs. It was first implemented in Windows 95, but optimized and best used in Windows NT, 2000, and XP. Here are the instructions to launch it in order to close nonresponsive programs and processes:
With Windows NT and 2000, press the keyboard combination "Ctrl+Alt+Delete" to get a window called "Windows Security". Some of the features may be disabled, depending on the network (corporate environment, etc.) conditions. Click "Task Manager" or press the key "T" to launch Task Manager. It is automatically set to a priority of "Above Normal". Task Manager can also be launched by right-clicking on the Windows Taskbar and selecting Task Manager.
With Windows XP, press the same keyboard combination, except Windows XP Home users will get Task Manager immediately without a "Windows Security" prompt. Windows XP Professional users have the same interface as that for Windows 2000 and NT.
The Task Manager can be used to monitor system performance (Performance tab), end applications (Applications tab), monitor and end processes (not recommended for non-techheads), and run new programs. It can help when a system appears to be frozen but is actually not.
With Windows NT and 2000, press the keyboard combination "Ctrl+Alt+Delete" to get a window called "Windows Security". Some of the features may be disabled, depending on the network (corporate environment, etc.) conditions. Click "Task Manager" or press the key "T" to launch Task Manager. It is automatically set to a priority of "Above Normal". Task Manager can also be launched by right-clicking on the Windows Taskbar and selecting Task Manager.
With Windows XP, press the same keyboard combination, except Windows XP Home users will get Task Manager immediately without a "Windows Security" prompt. Windows XP Professional users have the same interface as that for Windows 2000 and NT.
The Task Manager can be used to monitor system performance (Performance tab), end applications (Applications tab), monitor and end processes (not recommended for non-techheads), and run new programs. It can help when a system appears to be frozen but is actually not.
hmm, most of the ones I know have already been said but to check whether your computer is truly frozen or just taking a long time on a process press the numlock (or capslock) keys on your keyboard, if the keyboard LED lights up then its almost always a matter of waiting until your computer comes back to normal (or pressing ctrl+alt+del)
Latest Entries
SPEED UP YOUR INTERNET!
Lets start!
Open REGEDIT(Start->Run->Regedit)
Now you ll need to find a key on this location
"HKEY_LOCAL_MACHINE - Software - Microsoft - Windows -
Current Version - Explorer - RemoteComputer - NameSpace"
When you got there you ll need to delet this key (D6277990-4C6A-11CF-8D87-00AA0O60F5BF}
its because windows uses most of the bandwindth for microsoft's operations
Here's a pretty useless yet somewhat fun trick to rename the window title in IE- I've only tried this out on Win2k and Windows XP running IE6. I discovered it one day while curiously searching through the registry to see if I could change the "Internet Explorer provided by Abbot Laboratories" on my laptop (It's an ancient hand-me-down from my uncle)
This is a fairly safe trick. As long as you stick to the instructions here and don't go messing around with other Registry entries, you should be fine. However, just to be safe, you should always back-up your registry before doing any kind of manual editing.
1. Open the Registry Editor
Start -> Run -> type in regedit
2. Navigate to HKEY_CURRENT_USER\SOFTWARE\MICROSOFT\INTERNET EXPLORER\Main
NOTE: If the Window Title key already exists, you can skip step 3.
3. Right click somewhere in the right panel and choose new String Value. Name it Window Title
4. Double click on Window Title and where it says "Value data" put whatever you want your IE window title to say- For example, you could put something like "Bob's Magical Internet Explorer!" or maybe something slightly less lame. When you've made up your mind, hit ok.
5. Now open up IE and behold your own custom window title located to the right of whatever the name of the website you're viewing is. If you decide later you'd rather stick to the default "Microsoft Internet Explorer" title, just go back delete the Window Title value.
This is a fairly safe trick. As long as you stick to the instructions here and don't go messing around with other Registry entries, you should be fine. However, just to be safe, you should always back-up your registry before doing any kind of manual editing.
1. Open the Registry Editor
Start -> Run -> type in regedit
2. Navigate to HKEY_CURRENT_USER\SOFTWARE\MICROSOFT\INTERNET EXPLORER\Main
NOTE: If the Window Title key already exists, you can skip step 3.
3. Right click somewhere in the right panel and choose new String Value. Name it Window Title
4. Double click on Window Title and where it says "Value data" put whatever you want your IE window title to say- For example, you could put something like "Bob's Magical Internet Explorer!" or maybe something slightly less lame. When you've made up your mind, hit ok.
5. Now open up IE and behold your own custom window title located to the right of whatever the name of the website you're viewing is. If you decide later you'd rather stick to the default "Microsoft Internet Explorer" title, just go back delete the Window Title value.
this is copied from how to geek i think
If you press the windows key (in the keyboard) plus E, R, D or F you can open certain things, like:
E = EXPLORER
R = RUN
D = DESKTOP
F = FIND
M = MINIMIZE
This opens up a Windows Explorer window, a run box (like the one thats in the start menu), show desktop, a search window or minimize all windows open (which is not exacly the same that showing desktop).
Maybe a lot of people know this but if you dont, if you are running microsoft windows xp you have 2 messengers; windows messenger and microsoft network messenger (MSN messenger). You can access both, and have to sessions open at the same time.
Bring up yer run box and type:
msnmsgr - for msn messenger
msmsgs - for windows messenger
Note that windows messenger would not be able to upgrade, but once, and it will still be the 4.7 version.
For those who dont know: you can access almost every program from this run box (windows + r), for example:
winword - microsoft office word
excel - microsoft office excel
powerpnt - microsoft office power point
calc - windows calculator
notepad - =
firefox - =
www.address.com - opens default browser with the given address
regedit - windows registry
wmplayer - windows media player
osk - on screen keyboard
magnify - on screen windows zoom
taskmgr - task manager
services.msc - services
etc etc.
You can close a window by double clicking the icon at the upper side of the same window, on the left, like if you were going to close it normally on the 'X' but in the left side.
You can browse through windows with alt-tab, most of you would know, but what some of you wouldnt is that you can go backwards, shift-alt-tabbing.. (the same as for normal tabbing through a form in the web or the options of any given 'options' menu, shift + tab will go back instead of forth).
You can view the screen upside down. Go to start > run rand type "esc" (yes, the escape key up and left corner of keyboard). Then grabb your screen and turn it around (im sorry, thought this would be funny
).
WINDOWS TIPS COLLECTION
How to hack windows XP admin password
If you log into a limited account on your target machine and open up a dos prompt
then enter this set of commands Exactly:
cd\ *drops to root
cd\windows\system32 *directs to the system32 dir
mkdir temphack *creates the folder temphack
copy logon.scr temphack\logon.scr *backsup logon.scr
copy cmd.exe temphack\cmd.exe *backsup cmd.exe
del logon.scr *deletes original logon.scr
rename cmd.exe logon.scr *renames cmd.exe to logon.scr
exit *quits dos
Now what you have just done is told the computer to backup the command program
and the screen saver file, then edits the settings so when the machine boots the
screen saver you will get an unprotected dos prompt with out logging into XP.
Once this happens if you enter this command minus the quotes
"net user
If the Administrator Account is called Frank and you want the password blah enter this
"net user Frank blah"
and this changes the password on franks machine to blah and your in.
Have fun
p.s: dont forget to copy the contents of temphack back into the system32 dir to cover tracks
Registry Hacking
Display legal notice on startup:
Wanna tell your friends about the do's and dont's in your computer when they login in your absence. Well you can do it pretty easily by displaying a legal notice at system start up.
REGEDIT
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\policies\system]"legalnoticecaption"="enter your notice caption"
"legalnoticetext"="enter your legal notice text"
Automatic Administrator Login:
Well here's the trick which you can use to prove that Windows XP is not at all secure as multi-user operating system. Hacking the system registry from any account having access to system registry puts you in to the administrator account.
REGEDIT 4
[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows NT\CurrentVersion\Winlogon]
"AutoAdminLogon"="1"
No Shutdown:
Wanna play with your friends by removing the shutdown option from start menu in their computer.
Just hack it down !!!
Regedit
HKEY_CURRENT_USER\Software\Microsoft\Windows\CurrentVersion\Explorer
"NoClose"="DWORD:1"
Menu Delays:
Another minor and easy tweak to remove any delay from menus sliding out. For this you will need to use regedit (open regedit by going to Start -> Run..., then typing 'regedit' and pressing enter). The key you need to change is located in HKEY_CURRENT_USERControl PanelDesktop. The actual key is called MenuShowDelay - all you have to do is change the value to 0. Remember, you will have to re-boot your computer for this tweak to take effect.
GPEDIT.MSC And Autoplay
A great tweaking file that comes with XP is gpedit.msc. Go to Start -> Run... and then type in 'gpedit.msc' and press enter. This is effectively the Policies Editor, and it comes in handy often. For example, if you hate CD autoplay like I do and want to permanently disable it, you can use this tool to do so. Just run gpedit.msc, then go to Computer Configuration -> Administrative Templates -> System. In here you can see the value 'Turn Off Autoplay'. Right-click on it and then click 'Properties'.
Increasing options in add/remove programs:
Not a fan of MSN Messenger? don't want Windows Media Player on your system? Fair enough, but if you go to Add/Remove Programs in the Control Panel, by default none of Windows XP's 'built in' programs are visible. it's fairly easy to change, though... just open the file X:\Windows\inf\sysoc.inf (where X: is the drive letter where Windows XP is installed) in Notepad. You should see a section of the file something like this:
[Components]
NtComponents=ntoc.dll,NtOcSetupProc,,4
WBEM=ocgen.dll,OcEntry,wbemoc.inf,hide,7
Display=desk.cpl,DisplayOcSetupProc,,7
Fax=fxsocm.dll,FaxOcmSetupProc,fxsocm.inf,,7
NetOC=netoc.dll,NetOcSetupProc,netoc.inf,,7
iis=iis.dll,OcEntry,iis.inf,,7
com=comsetup.dll,OcEntry,comnt5.inf,hide,7
dtc=msdtcstp.dll,OcEntry,dtcnt5.inf,hide,7
IndexSrv_System = setupqry.dll,IndexSrv,setupqry.inf,,7
TerminalServer=TsOc.dll, HydraOc, TsOc.inf,hide,2
msmq=msmqocm.dll,MsmqOcm,msmqocm.inf,,6
ims=imsinsnt.dll,OcEntry,ims.inf,,7
fp_extensions=fp40ext.dll,FrontPage4Extensions,fp40ext.inf,,7
AutoUpdate=ocgen.dll,OcEntry,au.inf,hide,7
msmsgs=msgrocm.dll,OcEntry,msmsgs.inf,hide,7
RootAutoUpdate=ocgen.dll,OcEntry,rootau.inf,,7
IEAccess=ocgen.dll,OcEntry,ieaccess.inf,,7
This is a list of all components installed at the moment. I've taken the example of MSN Messenger - the program entry called 'msmsgs', third-last line. You can see the word 'hide' highlighted - this is the string which tells Windows not to display the component in the Add/Remove Programs list. Fix this up by simply deleting the word 'hide' like so:
msmsgs=msgrocm.dll,OcEntry,msmsgs.inf,hide,7
To this:
msmsgs=msgrocm.dll,OcEntry,msmsgs.inf,,7
Now, after restarting, you should be able to see MSN Messenger in the Add/Remove Programs list. If you want to be able to quickly view and remove all components, simply open the sysoc.inf file and do a global find and replace for the word ",hide" and replace it with a single comma ",".
Automatically Kill Programs At Shutdown:
don't you hate it when, while trying to shut down, you get message boxes telling you that a program is still running? Making it so that Windows automatically kills applications running is a snap. Simply navigate to the HKEY_CURRENT_USERControl PanelDesktop directory in the Registry, then alter the key AutoEndTasks to the value 1.
Speeding Up Share Viewing:
This is a great tweak. Before I found it, I was always smashing my head against the table waiting to view shares on other computers. Basically, when you connect to another computer with Windows XP, it checks for any Scheduled tasks on that computer - a fairly useless task, but one that can add up to 30 seconds of waiting on the other end - not good! Fortunately, it's fairly easy to disable this process. First, navigate to HKEY_LOCAL_MACHINE/Software/Microsoft/Windows/Current Version/Explorer/RemoteComputer/NameSpace in the Registry. Below that, there should be a key called {D6277990-4C6A-11CF-8D87-00AA0060F5BF}. Just delete this, and after a restart, Windows will no longer check for scheduled tasks - mucho performance improvement!
Create a Shortcut to Lock Your Computer
Leaving your computer in a hurry but you don’t want to log off? You can double-click a shortcut on your desktop to quickly lock the keyboard and display without using CTRL+ALT+DEL or a screen saver. To create a shortcut on your desktop to lock your computer: Right-click the desktop. Point to New, and then click Shortcut. The Create Shortcut Wizard opens. In the text box, type the following: rundll32.exe user32.dll,LockWorkStation Click Next. Enter a name for the shortcut. You can call it "Lock Workstation" or choose any name you like. Click Finish. You can also change the shortcut's icon (my personal favorite is the padlock icon in shell32.dll). To change the icon: Right click the shortcut and then select Properties. Click the Shortcut tab, and then click the Change Icon button. In the Look for icons in this file text box, type: Shell32.dll. Click OK. Select one of the icons from the list and then click OK You could also give it a shortcut keystroke such CTRL+ALT+L. This would save you only one keystroke from the normal command, but it could be more convenient.
Speed up Internet Explorer 6 Favorites
For some reason, the Favorites menu in IE 6 seems to slow down dramatically sometimes--I've noticed this happens when you install Tweak UI 1.33, for example, and when you use the preview tip to speed up the Start menu. But here's a fix for the problem that does work, though it's unclear why: Just open a command line window (Start button -> Run -> cmd) and type sfc, then hit ENTER. This command line runs the System File Checker, which performs a number of services, all of which are completely unrelated to IE 6. But there you go: It works.
Aspi
WinXP does not come with an Aspi layer. So far almost 90% of the problems with WinXP and CD burning software are Aspi layer problems. After installing WinXP, before installing any CD burning software do a few things first: 1. Open up "My computer" and right click on the CD Recorder. If your CD recorder was detected as a CD recorder there will be a tab called "Recording". On this tab uncheck ALL of the boxes. apply or OK out of it and close my computer. 2. Next install the standard Aspi layer for NT. Reboot when asked. That's is. after the reboot you can install any of the currently working CD recording applications with no problems. If using CD Creator do not install direct CD or Take two as they are currently incompatible but Roxio has promised a fix as soon as XP is released.
Friday, December 25
RoBo!!!!!!!!!!!!!!!!!
6-Legged Walking Robot Could Make You A Superhero
This walking hybrid human-machine is powered by fluidic muscle actuators, which helps reduce the friction and fatigue while navigating the bot to your destination of destruction. The legs of the bot are controlled with the users legs. When the human user lifts their right leg, the bot lifts the appropriate legs needed for smooth movement.
Robot Sports
Putter Bot Remote Controlled Golfer is certainly a good start. It may not be a fully automated robot per se, as it needs a human to command it. Let's face it, the robot is doing most of the work.
It is designed to line up the shot, and then the user can adjust the swing with whatever amount of power he or she requires. As you can see, it moves around on two triangular tracks that it must have borrowed from Number Five from Short Circuit.
Much of the information I have on this shows that this is someone's little home project, but I don't have a name. Personally, I think he has the next remote control toy sensation. That, or what would happen if Tiger Woods lost his arms in a tragic car accident. Perhaps this inventor should design something for long drives as well.
Trossen Robotics offer new MechRC Humanoid Robot
Trossen Robotics will be making available its new MechRC Humanoid Robot to the masses in the US, and parents can breath easy since this Christmas present won't break the $1,000 barrier in terms of pricing. That doesn't mean it is affordable for everyone though, since it is still pretty pricey at $599.99 – definitely not an impulse purchase considering how everyone else is tightening their wallets to weather the current global economic meltdown.
High torque metal gear servos, LiPo batteries for longer run times, a fluid 3D visual software programming interface for easy custom motions, and a remote control unit are included. Everything you need to have you own walking robot is included in this ready-to-walk kit! With over a hundred pre-installed motions and sounds you can get this robot throwing some dance floor shapes or some killer fighting moves straight from the box.
Telepresence Robot
The Anybot telepresence robot is a videophone with a bit of a difference. The screen and phone are incorporated into a 2 wheeled human sized robot.
Like a Segwat the Anybot uses the same sort of technology to always remain upright even when bending (I'm guessing this is so it can look down on your minions even when you're away from the office).
It has a top speed of 6 MPH, a built in laser pointer (maybe a gun in later versions), 2 cameras and full duplex audio. It's a cool idea but somewhat big brotherish IMO.
The Machine bOb battery bot
These are designed by Wayne Poulton who created both Machine bOb who is shown here, as well as his protector Machine PP3. Machine bOb is said to be a skittery little guy, who can wheel his way across your desk. All the while lighting the way with his bright eyes. To keep him out of trouble though you'll want PP3, which was the first of the designer's creations. You can pick them both up for the same price on Anti-Gravity. They're sold for £9.99 each.
Robot Money Box guards
This is where the Robot Money Box comes in. When you put money in the bank, it can actually keep track of how much you put in. I'm not certain how it does this. I doubt it has advanced sensors or anything. Perhaps it can somehow counts as you put it your coins or dollars in.
Another feature that makes the Robot Money box different from your average piggy bank is that it praises you for saving money. Not only that, but you can make target goals for saving, and it will encourage you for making them.
There is one other feature that my source and the Product Page are very vague about. Apparently, the Robot Money Box "may even try to stop you if you try to take anything out".
Solar Climbing Orangutan
Want to have a toy that goes on and on and on without the use of Energizer or Duracell batteries? That's not a problem with the Solar Powered Orangutan, although it does look like a carved out piece of Lego from certain angles. All you need to do is set this Orangutan on a piece of string, expose it to some light and voila – it will get to work, climbing up to the very pinnacle according to its ability. You will need some assembly with this toy though, and it will take you approximately 20 minutes to complete the whole setup. The only tool you need? A simple screwdriver. $14.99 is the asking price for this piece of mindless fun.
RoBo Rajini!!!
re... Toyota’s Mobility Robot and Violin-playing Robot to be rolled out by 2010
Asimo - lets Control via mind
Flossie - the Motorcyle-testing Robot
Ropid Robot can run and jump
Wall Climbing R/C Insect
Anaconda Robot Fire Fighting Snake
Toyota’s Mobility Robot and Violin-playing Robot to be rolled out by 2010
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